The present invention relates to inspection of an exposure mask to be used in a lithography step for semiconductor integrated circuit devices.
The recent price cutting of memory devices leads to rapid acceleration of the miniaturization of semiconductor devices. This trend of miniaturization is seen not only on memory devices but also on logic devices such as an RISC chip which demand a fast operation. The miniaturization of some logic devices comes ahead of that of memory devices. That is, time has come when logic devices play the role of the technology driver for the miniaturization process that memory devices have served as. This trend makes it more and more important to develop the miniaturization process technology in consideration of the device characteristics of logic devices.
As miniaturization is accelerated, influence of a variation in mask CD (critical dimension) on the CD of wafer patterns can no longer be neglected. This demands more precise mask specifications (CD, defect, etc.) at the time of mask shipment becomes severe.
Conventionally, the planar specifications of the mask CDs for leading large-scale integrated memory devices like DRAMs have been verified by extracting several portions to be measured (hereinafter called "to-be-measured portions") from a memory cell section and measuring the CD of the mask at each to-be-measured portion. This scheme has been employed because the pattern of a memory cell section should meet more precise size requirements than other patterns, occupies a certain portion (50 to 60%) of the inner area of the chip and is basically formed by repetitive patterns, which makes determination of the size specifications relatively easy.
By way of contrast, a logic device basically has a random circuit pattern which, unlike the memory cell section of a memory device, is hardly formed by repetitive patterns. Therefore, the aforementioned scheme for memory devices of extracting proper to-be-measured portions from a memory cell section and measuring the CD of a mask at each to-be-measured portion cannot fundamentally be used for logic devices.
In view of such a situation, a scheme of arranging repetitive patterns for measurement, such as line and space (L/S) patterns at a kerf portion (the boundary between chips) and measuring the sizes of those patterns to verify the mask CD across the mask has been employed for existing logic devices.
However, the scheme of arranging L/S patterns for measurement at the kerf portion cannot verify the specifications of the mask CD across the mask of an exposure mask by the pattern CD of a portion that should be really verified in terms of process and device.
In addition, basically a kerf portion often becomes an edge portion of an exposure mask, so that the pattern CD in an exposure area which serves as an actual device cannot be monitored.